1. Field of the Invention
The present invention relates generally to methods of manufacturing semiconductor devices and particularly to methods of manufacturing semiconductor devices including a step of dry etch and wet etch provided successively. The present invention also relates to methods of manufacturing flash memories including a step of dry etch and wet etch provided successively. The present invention also relates to flash memories manufactured by such manufacturing methods. The present invention also relates to methods of manufacturing static random access memories (SRAMs).
2. Description of the Background Art
FIG. 11 shows a cross section of a memory cell of a conventional flash memory.
Referring to FIG. 11, in a surface of a semiconductor substrate containing a p dopant a p doped region 1a is formed. On semiconductor substrate 1 a floating gate 4 is formed with a tunnel oxide film 3 posed therebetween. In a surface of p doped region 1a on opposite sides of floating gate 4, source/drain regions 2a and 2b are formed. On floating gate 4 an insulation film 8 is formed. On insulation film 8 a control gate 9 is formed. On semiconductor substrate 1, insulation layers 10 and 11 are formed such that they cover control gate 9.
The flash memory operates as described below.
In write operation, drain region 2b receives a drain voltage of approximately 6 to 8V and control gate 9 receives a gate voltage of approximately 10 to 15V. Source region 2a and semiconductor substrate 1 have a voltage held at a ground voltage. As such a current of several hundreds xcexcA flows through a channel region 2c. Of the electrons flowing from source region 2a to drain region 2b, the electrons accelerated in a vicinity of drain region 2b becomes those with high energy (i.e., hot electrons). Such electrons flow in a direction indicated by an arrow 12 due to an electric field resulting from the gate voltage applied to control gate 9, and are thus introduced into floating gate 4. As such electrons accumulate in floating gate 4, the transistor""s threshold voltage is increased. Such threshold voltage higher than a predetermined value corresponds to a state. referred to as xe2x80x9c0xe2x80x9d.
In data erase operation, initially source region 2a receives a source voltage of approximately 10 to 15V and control gate 9 and semiconductor substrate 1 are held at a ground potential. Then, drain region 2b is floated, and an electric field resulting from the source voltage applied to source region 2a allows the electrons accumulated in floating gate 4 to flow in a direction indicated by an arrow 13, passing through tunnel insulation film 3 into semiconductor substrate 1. When the electrons accumulated internal to floating gate 4 are extracted, the transistor""s threshold is increased. Such threshold voltage lower than a predetermined value corresponds to a state with data erased, referred to as xe2x80x9c1xe2x80x9d. Such erasure allows collective erasure of memory cells formed in a single semiconductor device. In read operation, control gate 9 receives a gate voltage of approximately 5V and drain region 2b receives a drain voltage of approximately 1 to 2V, and then if channel region 2c passes current or the transistor is ON then data is determined to be xe2x80x9c1xe2x80x9d and if channel region 2c does not pass current or the transistor is OFF then data is determined to be xe2x80x9c0xe2x80x9d.
A flash memory configured as described above is manufactured by a method as described below.
Initially, as shown in FIG. 12, an element isolating oxide film is formed on a semiconductor substrate 1 of monocrystalline silicon to isolate memory cells from each other, isolate transistors in peripheral circuitry from each other, and isolate the cells and the peripheral transistors from each other. Then p doped region 1a in which memory cells are to be formed is formed. Then the substrate""s upper surface is oxidized to provide a tunnel insulation film 3 of silicon dioxide (SiO2).
Referring to FIG. 13, chemical vapor deposition (CVD) is employed to deposit polycrystalline silicon on tunnel insulation film 3. The polycrystalline silicon only in the memory cell region is etched in an x direction (a direction horizontal relative to the plane of the figure, not shown) to form a floating gate 4. Then, chemical vapor deposition is similarly employed to form an insulation film 8, such as a silicon nitride (SiN) film, a silicon oxide film. Then, insulation film 8, the polycrystalline silicon and tunnel insulation film 3 are removed in the peripheral-circuitry region. Then, as in forming polycrystalline silicon (floating gate) 4, chemical vapor deposition is employed to deposit polycrystalline silicon serving as control gate 9.
Then, as shown in FIG. 14, on a region with polycrystalline silicon that is desired as a gate electrode a patterned photoresist 14 is provided in a y direction (a direction vertical relative to the plane of the figure). With patterned photoresist 14 used as a mask, the region is anisotropically etched to expose a surface of tunnel insulation film 3.
Then, patterned resist 14 is for example plasma-ashed and thus removed.
As shown in FIG. 15, dopant ions are introduced in a direction indicated by an arrow 15 to form at an upper portion of p doped region 1a heavily n doped regions (source/drain regions) 2a and 2b higher in dopant concentration than p doped region 1a. Then, as shown in FIG. 11, chemical vapor deposition or the like is employed to provide insulation layers 10 and 11 formed of silicon oxide film and serving as a passivation film to complete a flash memory.
The semiconductor device manufacturing method as above has a disadvantage described below with reference to simplified drawings.
As shown in FIG. 16, on a silicon substrate 1 a SiO2 film 2 is formed. On SiO2 film 2 a polysilicon film 3 is deposited. On polysilicon film 3 a patterned photoresist 4 is provided by photolithography. With patterned resist 4 used as a mask, polysilicon film 3 is dry-etched and then successively SiO2 film 2 is etched with a hydrofluoric acid solution.
In the hydroflouric acid solution process, however, when polysilicon film 3 is dry-etched an altered surface layer 5 of patterned photoresist 4 is removed, as shown in FIG. 17. Removed surface layer 5 of the resist adheres onto silicon substrate 1 and thus disadvantageously prevents the underlying SiO2 film 2 from being etched. Furthermore, removed surface layer 5 of the resist disadvantageously flows into the hydrofluoric acid treatment bath and as a foreign matter contaminates the bath.
Furthermore, such problem tends to occur particularly when polysilicon is etched with chloride type gas.
Furthermore, such problem also tends to occur when with a polysilicon film having an insulation film such as SiO2 film, SiN film deposited thereon the SiO2/SiN film is dry-etched, the polysilicon film is dry-etched and the SiO2 film is then wet-etched with hydrofluoric acid solution successively.
The present invention has been made to solve such disadvantages as described above.
The present invention contemplates an improved semiconductor manufacturing method capable of preventing removal of an altered surface layer of a patterned photoresist.
The present invention also contemplates an improved flash memory manufacturing method preventing removal of an altered surface layer of a patterned photoresist.
The present invention also contemplates an improved static random access memory manufacturing method preventing removal of an altered surface layer of a patterned photoresist.
In accordance with the present invention in one aspect a semiconductor device manufacturing method includes the steps of: initially forming on a semiconductor substrate an insulation film and a conductive layer successively by either deposition or deposition followed by patterning (step 1); forming a patterned resist on the conductive layer (step 2); with the patterned resist used as a mask, dry-etching the conductive layer (step 3); partially removing a surface layer of the patterned resist (step 4); and with the patterned resist used as a mask, etching the insulation film.
In accordance with the present invention, partially removing a surface layer of the patterned resist allows removal of an altered surface of the patterned resist.
In accordance with the present invention in a second aspect a semiconductor device manufacturing method provides step 4 using an O2 plasma etch to partially remove a surface layer of the patterned resist.
In accordance with the present invention in a third aspect a semiconductor device manufacturing method includes using an O2 mixed gas to dry-etch the conductive layer in step 3 and thus providing step 4 in the sequence of dry-etching the conductive layer.
In accordance with the present invention in a fourth aspect a semiconductor device manufacturing method includes the steps of: forming on a semiconductor substrate an insulation film and a conductive layer successively by either deposition or deposition followed by patterning (step 1); forming a patterned resist on the conductive layer (step 2); with the patterned resist used as a mask, dry-etching the conductive layer (step 3); joining together an altered surface layer of the patterned resist and a normal layer of the patterned resist underlying the surface thereof, and thus preventing the altered layer and the normal layer from being removed (step 4); and with the patterned resist used as a mask, etching the insulation film (step 5).
In accordance with the present invention, an altered surface layer of a patterned resist and a normal layer of the patterned resist underlying the surface thereof can be joined together and thus prevented from being removed.
In accordance with the present invention in a fifth aspect a semiconductor device manufacturing method includes in step 4 the step of illuminating a surface of the patterned resist in a N2 ambient with a deep ultraviolet light and subsequently thermally processing the same.
In accordance with the present invention in a sixth aspect a semiconductor device manufacturing method includes in step 4 the step of illuminating a surface of the patterned resist in a dry air with a deep ultraviolet light and subsequently thermally processing the patterned resist.
In accordance with the present invention in a seventh aspect a semiconductor device manufacturing method provides step 4 by thermally processing the patterned resist in a dry air.
In accordance with the present invention in an eighth aspect a flash memory manufacturing method includes the steps of: forming on a surface of a semiconductor substrate an isolating oxide film isolating a memory cell region and a peripheral circuitry region from each other (step 1); forming a tunnel oxide film on a surface of the semiconductor substrate (step 2); forming a first polysilicon layer on the tunnel oxide film (step 3); patterning the tunnel oxide film and the first polysilicon layer as desired (step 4); forming an insulation film on the first polysilicon layer (step 5); forming on the insulation film a patterned resist having an end positioned on the isolating oxide film and covering only the memory cell region (step 6); with the patterned resist used as a mask, dry-etching and thus removing the insulation film and the first polysilicon layer that overlie the peripheral circuitry region (step 7); partially removing a surface of the patterned resist (step 8); with the patterned resist used as a mask, removing the tunnel oxide film overlying the peripheral circuitry region (step 9); removing the patterned resist (step 10); forming on the semiconductor substrate and on the peripheral circuitry region a gate oxide film for a peripheral transistor (step 11); forming a second polysilicon layer on the semiconductor substrate (step 12); forming on the second polysilicon layer an oxide film used as an etching mask (step 13); forming a control gate in the memory cell region and forming a transistor gate for the peripheral circuitry (step 14); and patterning the insulation film and the first polysilicon layer and forming a floating gate (step 15).
In accordance with the present invention, partially removing a surface layer of a patterned resist allows removal of an altered surface layer of the patterned resist.
In accordance with the present invention in a ninth aspect a flash memory includes a semiconductor substrate. On the semiconductor substrate a dummy gate region is provided. On the semiconductor substrate a memory cell region and a peripheral circuitry region are provided to sandwich the dummy gate region. The dummy gate region includes an isolating oxide film formed on the semiconductor substrate. On the isolating oxide film a first conductive layer is provided having an end closer to the peripheral circuitry region that recedes towards the memory cell region. On the first conductive layer an insulation layer is provided having an end closer to the peripheral circuitry region that recedes towards the memory cell region. On the isolating oxide film a second conductive layer is provided covering the first conductive layer and the insulation layer.
In accordance with the present invention in a tenth aspect a semiconductor device manufacturing method in the first or fourth aspect uses a polysilicon film as the conductive layer and dry-etches the conductive layer with a chloride-type gas.
In accordance with the present invention in an eleventh aspect, a flash memory manufacturing method in the eighth aspect at step 6 uses a chlorine gas to dry-etch the patterned resist.
In accordance with the present invention in a twelfth aspect a semiconductor device manufacturing method include the steps of: initially forming on a semiconductor substrate an insulation film and a conductive layer successively (step 1); forming a second insulation film (step 2); forming a patterned resist on the second insulation film (step 3); with the patterned resist used as a mask, dry-etching the second insulation film and the conductive layer (step 4); partially removing a surface layer of the patterned resist (step 5); and with the patterned resist used as a mask, etching the insulation film (step 6).
In accordance with the present invention in a thirteenth aspect a semiconductor manufacturing method provides step 5 using an O2 plasma etch to partially remove a surface of the patterned resist.
In accordance with the present invention in a fourteenth aspect a semiconductor device manufacturing method includes step 4 using an O2 mixed gas to dry-etch the second insulation film and the conductive layer and thus provides step 5 in the sequence of dry-etching the conductive layer.
In accordance with the present invention in a fifteenth aspect a semiconductor device manufacturing method includes the steps of: initially forming on a semiconductor substrate an insulation film and a conductive layer successively (step 1); forming a second insulation film (step 2); forming a patterned resist on the conductive layer (step 3); with the patterned resist used as a mask, dry-etching the conductive layer (step 4); joining together an altered surface layer of the patterned resist and a normal layer of the patterned resist underlying the surface layer thereof and thus preventing the altered surface layer and the normal layer from being removed (step 5); and with the patterned resist used as a mask, etching the insulation film (step 6).
In accordance with the present invention in a sixteenth aspect a semiconductor device manufacturing method includes in step 5 the step of illuminating a surface of the patterned resist in a N2 ambient with a deep ultraviolet light and subsequently thermally processing the patterned resist.
In accordance with the present invention in a seventeenth aspect a semiconductor device manufacturing method includes in step 5 the step of illuminating a surface of the patterned resist in dry air with a deep ultraviolet light and subsequently thermally processing the patterned resist.
In accordance with the present invention in an eighteenth aspect a semiconductor manufacturing method provides step 5 thermally processing the patterned resist in a dry air.
In accordance with the present invention in a nineteenth aspect a flash memory manufacturing method includes the steps of: initially forming on a surface of a semiconductor substrate an isolating oxide film isolating a memory cell region and a peripheral circuitry region from each other (step 1); forming a tunnel oxide film on a surface of the semiconductor substrate (step 2); forming a first polysilicon layer on the tunnel oxide film (step 3); patterning the tunnel oxide film and the first polysilicon layer as desired (step 4); forming an insulation film on the first polysilicon layer (step 5); forming on the insulation film a patterned resist having an end positioned on the isolating oxide film and covering only the memory cell region (step 6); with the patterned resist used as a mask, dry-etching and thus removing the insulation film and the first polysilicon layer that overlie the peripheral circuitry region (step 7); using O2 plasma to etch and thus partially remove a surface layer of the patterned resist (step 8); with the patterned resist used as a mask, removing the tunnel oxide film overlying the peripheral circuitry region (step 9); removing the patterned resist (step 10); forming on the semiconductor substrate and on the peripheral circuitry region a gate oxide film for a peripheral transistor (step 11); forming a second polysilicon layer on the semiconductor substrate (step 12); forming on the second polysilicon layer an oxide film used as an etching mask (step 13); forming a control gate. in the memory cell region and forming a transistor gate for the peripheral circuitry (step 14); and patterning the insulation film and the first polysilicon layer and forming a floating gate (step 15).
In accordance with the present invention in a twentieth aspect a flash memory manufacturing method is characterized in that in step 7 the insulation film and the first polysilicon layer are dry-etched with an O2 mixed gas and that in step 8 the patterned resist""s surface layer is partially removed in the dry-etching sequence.
In accordance with the present invention in a twenty-first aspect a flash memory manufacturing method includes the steps of: initially forming on a surface of a semiconductor substrate an isolating oxide film isolating a memory cell region and a peripheral circuitry region from each other (step 1); forming a tunnel oxide film on a surface of the semiconductor substrate (step 2); forming a first polysilicon on the tunnel oxide film (step 3); patterning the tunnel oxide film and the first polysilicon layer, as desired (step 4); forming an insulation film on the first polysilicon layer (step 5); forming on the isolation film a patterned resist having an end positioned on the isolating oxide film and covering only the memory cell region (step 6); with the patterned resist used as a mask, dry-etching and thus removing the insulation film and the first polysilicon layer that overlie on the peripheral circuitry region (step 7); joining together an altered surface layer of the patterned resist and a normal portion of the patterned resist underlying the surface layer thereof and thus preventing the altered surface layer and the underlying normal portion from being removed (step 8); with the patterned resist used as a mask, removing the tunnel oxide film overlying the peripheral circuitry region (step 9); removing the patterned resist (step 10); forming on the semiconductor substrate and on the peripheral circuitry region a gate oxide film for a peripheral transistor (step 11); forming a second polysilicon layer on the semiconductor substrate (step 12); forming on the second polysilicon layer an oxide film used as an etching mask (step 13); forming a control gate in the memory cell region and forming a transistor gate for the peripheral circuitry (step 14); and patterning the insulation film and the first polysilicon layer and forming a floating gate (step 15).
In accordance with the present invention in a twenty-second aspect a flash memory manufacturing method includes step 8 illuminating a surface of the patterned resist in a N2 ambient with a deep ultraviolet light and thermally processing the patterned resist.
In accordance with the present invention in a twenty-third aspect a flash memory manufacturing method includes step 8 illuminating a surface of the patterned resist in a dry air with a deep ultraviolet light and thermally processing the patterned resist.
In accordance with the present invention in a twenty-fourth aspect a flash memory manufacturing method includes step 8 thermally processing the patterned resist in a dry air.
In accordance with the present invention in a twenty-fifth aspect an SRAM manufacturing method includes the steps of: initially forming an isolating oxide film on a surface of a semiconductor substrate (step 1); depositing a gate oxide film on the semiconductor substrate (step 2); depositing a first polysilicon layer on the gate oxide film (step 3); forming a patterned resist having an opening extending from an active region to the isolating oxide film (step 4); with the patterned resist used as a mask, dryetching and thus removing the first polysilicon layer (step 5); partially removing a surface layer of the patterned resist (step 6); again with the patterned resist used as a mask, removing the gate oxide film at a bottom of the patterned resist (step 7); removing the patterned resist (step 8); forming a second polysilicon layer (step 9); forming of resist a pattern providing a gate electrode of an access transistor, a pattern providing a gate electrode of a driver transistor and a pattern providing a gate electrode of a transistor for peripheral circuitry (step 10); with the patterned resist used as a mask, dry-etching the first and second polysilicon layers (step 11); removing the patterned resist (step 12); doping only an n region with an n dopant (step 13); and thermally processing a resultant product (step 14).
In accordance with the present invention in a twenty-sixth aspect an SRAM manufacturing method includes step 6 using an O2 plasma etch and thus partially remove a surface of the patterned resist.
In accordance with the present invention in a twenty-seventh aspect an SRAM manufacturing method includes in step 5 using an O2 mixed gas to dry-etch the first polysilicon layer and in step 6 partially removing a surface layer of the patterned resist in the dry-etching sequence.
In accordance with the present invention in a twenty-eighth aspect an SRAM manufacturing method includes the steps of: initially forming an isolating oxide film on a surface of a semiconductor substrate (step 1); depositing a gate oxide film on the semiconductor substrate (step 2); depositing a first polysilicon layer on the gate oxide film (step 3); forming a patterned resist having an opening extending from an active region to the isolating oxide film (step 4); with the patterned resist used as a mask, dryetching and thus removing the first polysilicon layer (step 5); joining together an altered surface layer of the patterned resist and a normal portion of the patterned resist underlying the altered surface layer thereof and thus preventing the altered surface layer and the normal portion from being removed (step 6); again with the patterned resist used as a mask, removing the gate oxide film at a bottom of the pattern (step 7); removing the patterned resist (step 8); forming a second polysilicon layer (step 9); forming of resist a pattern providing a gate electrode of an access transistor, a pattern providing a gate electrode of a driver transistor and a pattern providing a gate electrode of a transistor for peripheral circuitry (step 10); with the patterned resist used as a mask, dry-etching the first and second polysilicon layers (step 11); removing the patterned resist (step 12); doping only an n region with an n dopant (step 13); and thermally processing a resultant product (step 14).
In accordance with the present invention in a twenty-ninth aspect an SRAM manufacturing method includes in step 6 the step of illuminating a surface of the patterned resist in a N2 ambient with a deep ultraviolet light and successively thermally processing the patterned resist.
In accordance with the present invention in a thirtieth aspect an SRAM manufacturing method includes in step 6 the step of illuminating a surface of the patterned resist in a dry air with a deep ultraviolet light and successively thermally processing the patterned resist.
In accordance with the present invention in a thirty-first aspect an SRAM manufacturing method includes step 6 thermally processing the patterned resist in a dry air.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.